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TOWARDS EFFICIENT AND SCALABLE MACHINE LEARNING FOR FUTURE NEURAL INTERFACES

dc.contributor.authorZhu, Bingzhao
dc.contributor.chairXu, Chunhuien_US
dc.contributor.committeeMemberDe Sa, Christopheren_US
dc.contributor.committeeMemberShoaran, Mahsaen_US
dc.date.accessioned2024-04-05T18:48:47Z
dc.date.available2024-04-05T18:48:47Z
dc.date.issued2023-08
dc.description210 pagesen_US
dc.description.abstractClosed-loop approaches in systems neuroscience and therapeutic stimulation have the potential to revolutionize our understanding of the brain and develop novel neuromodulation therapies for restoring lost functions. Neural interfaceswith capabilities such as multi-channel neural recording, on-site signal processing, rapid symptom detection, and closed-loop stimulation are crucial for enabling these innovative treatments. However, current closed-loop neural interfaces are limited by their simplicity and lack of sufficient on-chip processing and intelligence. This dissertation focuses on the development of next-generation neural decoders for closed-loop neural interfaces, utilizing on-chip machine learning to detect and suppress symptoms of neurological disorders. These neural decoders offer high versatility, low power consumption, minimal on-chip area, and robustness against neural signal fluctuations. Chapter 2 explores migraine state classification using somatosensory evoked potentials, an emerging application for neural interfaces. In Chapter 3, we introduce a resource-efficient oblique tree model that enables low-power, memory-efficient classifiers for realtime neurological disease detection and motor decoding. Chapter 4 presents a novel Tree in Tree decision graph model with applicability beyond neural data, demonstrating success in general tabular prediction tasks. In Chapter 5, we propose an adaptive machine learning-based decoder to compensate for fluctuations in neural signals during test time. The dissertation concludes with a discussion of future research directions for on-chip neural decoders.en_US
dc.identifier.doihttps://doi.org/10.7298/h6sz-ga92
dc.identifier.otherZhu_cornellgrad_0058F_13766
dc.identifier.otherhttp://dissertations.umi.com/cornellgrad:13766
dc.identifier.urihttps://hdl.handle.net/1813/114825
dc.language.isoen
dc.subjectIntegrated Circuiten_US
dc.subjectMachine Learningen_US
dc.subjectNeural Interfacesen_US
dc.subjectNeurological Disorderen_US
dc.titleTOWARDS EFFICIENT AND SCALABLE MACHINE LEARNING FOR FUTURE NEURAL INTERFACESen_US
dc.typedissertation or thesisen_US
dcterms.licensehttps://hdl.handle.net/1813/59810.2
thesis.degree.disciplineApplied Physics
thesis.degree.grantorCornell University
thesis.degree.levelDoctor of Philosophy
thesis.degree.namePh. D., Applied Physics

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