Using Information Flow to Design an ISA that Controls Timing Channels

Zagieboylo, Drew; Suh, Gookwon Edward; Myers, Andrew C.

Using Information Flow to Design an ISA that Controls Timing Channels

dc.contributor.author	Zagieboylo, Drew
dc.contributor.author	Suh, Gookwon Edward
dc.contributor.author	Myers, Andrew C.
dc.date.accessioned	2019-06-17T17:49:48Z
dc.date.available	2019-06-17T17:49:48Z
dc.date.issued	2019
dc.description.abstract	Information-flow control (IFC) enforcing languages can provide high assurance that software does not leak information or allow an attacker to influence critical systems. IFC hardware description languages have also been used to design secure circuits that eliminate timing channels. However, there remains a gap between IFC hardware and software; these two components are built independently with no abstraction for how to compose their security guarantees. This paper presents a proposal for an instruction set architecture (ISA) that can provide the appropriate abstraction for joining hardware and software IFC mechanisms. Our ISA describes a RISC-V processor that tracks information-flow labels at run time and uses these labels to eliminate or mitigate timing channels. To make the ISA more practical, it allows constrained downgrading of information; it permits trading off security for performance; and still offers control primitives such as system calls. We prove timing-sensitive noninterference modulo downgrading and nonmalleability for programs executing our ISA. This involves novel restrictions on the mutability of labels beyond previous dynamic IFC systems. Furthermore, we define specific security conditions which correct hardware can implement to provide software-level security and sketch how such hardware may be designed and verified.	en_US
dc.description.sponsorship	NSF grant CNS-1513797 DARPA contract HR0011-18-C-0014	en_US
dc.identifier.uri	https://hdl.handle.net/1813/66488
dc.language.iso	en_US	en_US
dc.rights	Attribution-NonCommercial-ShareAlike 4.0 International	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-sa/4.0/	*
dc.subject	Security	en_US
dc.subject	Hardware Architecture	en_US
dc.subject	Side Channels	en_US
dc.subject	Information Flow	en_US
dc.title	Using Information Flow to Design an ISA that Controls Timing Channels	en_US
dc.type	technical report	en_US

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Using Information Flow to Design an ISA that Controls Timing Channels

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